Convergence of Artificial Intelligence and the Internet of Things by Unknown

Author:Unknown
Language: eng
Format: epub
ISBN: 9783030449070
Publisher: Springer International Publishing

The flexibility of the device is the level of how easy is to change its functionality. CPU is the most flexible, but exhibits the lowest performance and energy efficiency. ASICs are the less flexible because the function is hardwired in the silicon fabric. FPGAs are more flexible than ASICs because the hardware can be reconfigured for a specific function but less flexible than CPU or GPU since software is easier to modify. GPUs offer the best performance among the flexible devices and are cheaper than FPGAs. This is why they are predominantly used for deep learning on the cloud. However, in spite of their high energy efficiency, they have high energy consumption because of its massive parallel processing. To keep the high performance computing but with a reduced energy consumption companies are deploying ASIC at the cost of loosing the flexibility. This is a risk since deep learning algorithms are still evolving and looking for the best algorithmic solutions.

GPU are widely used for training in the cloud because they are flexible and its many core architecture and high memory bandwidth offers computation powers over 100 TFLOPs. Recent GPUs include 16-bit floating-point operations together with single and double precision floating-point. While the last can be used for training, 16-bit floating-point units are enough for inference, which improves the inference efficiency. ASIC circuits for specific deep learning models increase performance and power efficiency at the cost of reduced flexibility. The latest Tensor Processing Unit (TPU) from Google is an example of a chip for both training and inference with 420 TFLOPs and 2.4 TBytes of memory bandwidth at very high power efficiency.

GPUs and ASICs are good platforms for cloud computing but the high energy consumption of GPUs and fixed architecture of ASIC make it unfeasible for edge devices with tight energy, cost and flexibility constraints. This barrier pushed edge devices to microcontrollers, CPUs and DSP (Digital Signal Processor). The problem is that these programmable devices cannot guarantee the required performance of the new machine learning applications, in particular deep learning. A tradeoff between flexibility and specificity leaves designers between better performance and lower device cost [46]. This leaves space for FPGAs as devices for edge computing.

Field programmable gate arrays can be reprogrammed to implement a specific deep learning architecture improving the performance while being flexible. At this development stage of deep learning algorithms, flexible and high-performance devices with low power requirements, like FPGAs, are the appropriate target device. Recently, with the introduction of SoC (System-on-Chip) FPGAs, hardware/software systems have reduced design times while increasing the programmability with a processor and the performance with integrated reconfigurable logic.

In the following sections, an overview of devices applied to deep learning at the edge is given.

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